1. Field of the Invention
The present invention relates to a wafer dicing process for optical electronic packing, and more particularly to a wafer dicing process for optical electronic packing, which elongates the lifetime of the dicing saws and forms high quality cutting plane and a precise backside dicing reference coordinate.
2. Description of the Prior Art
In the field of optical electronic packing, a package has to perform multiple functions. Therefore the structure of the package in wafer level packing possibly consists of several materials. FIG. 1A and FIG. 1B schematically illustrate a traditional wafer dicing process for optical electronic packing. The structure of the package contains three wafers with different materials and functions, including a first wafer p10 (glass wafer), a third wafer p30 (Complementary Metal-Oxide Semiconductor, CMOS) wafer, and a second wafer p20 (interposer wafer) which separates the first wafer p10 a distance from the third wafer p30. These three wafers form a laminated structure for optical electronic packing. The traditional method to dice the packed wafer is cutting through by a single dicing saw p40. By using this method, the cutting plane of the wafer package is not smooth and forming a rough plane p31. It not only affects the cutting precision, but also increases the wearing rate of the dicing saw p40 by using this single dicing saw to cut through the laminated waters.